Video Codec

A YAPI system level optimized parallel model of a H.264/AVC video encoder

Computational Modeling / Video Coding / Video Codec / Chip / System on a Chip / Embedded System

VLSI architecture for a low-power video codec system

Vlsi Design / Microelectronics / Video Coding / Hardware/Software Co-Design / Rapid Prototyping / Motion estimation / VERY LARGE SCALE INTEGRATED CIRCUITS / Power Consumption / Circuit Complexity / Low Power / Video Codec / Data transfer / Full Text Search / Cost Function / High Efficiency / Electrical And Electronic Engineering / System Modelling / Performance Measure / Direct Memory Access / VLSI architecture / Motion estimation / VERY LARGE SCALE INTEGRATED CIRCUITS / Power Consumption / Circuit Complexity / Low Power / Video Codec / Data transfer / Full Text Search / Cost Function / High Efficiency / Electrical And Electronic Engineering / System Modelling / Performance Measure / Direct Memory Access / VLSI architecture

Assessment of H.264 coded panorama sequences

Video Coding / Video Compression / Video Streaming / Wireless Network / Video Quality / Spatial Information / Temporal Information Extraction / Video Codec / Human Perception / Signal to Noise Ratio / Quality Measures / Spatial Information / Temporal Information Extraction / Video Codec / Human Perception / Signal to Noise Ratio / Quality Measures

A YAPI system level optimized parallel model of a H.264/AVC video encoder

Computational Modeling / Video Coding / Video Codec / Chip / System on a Chip / Embedded System
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